Hardware requirements for spike-processing neural networks

Experimental results suggest that the rime structure of neuronal spike trains can be relevant in neuronal signal processing. In view of these results, a shift of interest from analog neural networks to spike-processing neural networks has been observed. For tasks like image processing the simulation of these networks has to be performed with the speed of biological neural networks, We investigated the performance of available hardware and showed, that the required performance for large networks could not be achieved. According to these results we formulated concepts for the design of dedicated hardware for spike-processing neurons. For an efficient hardware implementation it is necessary to know the requisite precision for computations. Through simulations with fixed-point numbers we examined the effects of word length limitation on the behaviour of a spike-processing network. The network was able to perform its basic task as long as the word length does not fail below a certain limit. On this basis we derived conditions for the lower bound of the requisite word length.