共 10 条
- [6] A 45nm logic technology with high-k plus metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging [J]. 2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 247 - +
- [7] Narayanan V., 2006, P VLSI TECHN S, P224