A TUNABLE CMOS-DRAM VOLTAGE LIMITER WITH STABILIZED FEEDBACK-AMPLIFIER

This paper presents two developments for a CMOS-DRAM voltage limiter: a precise internal-voltage generator, and a stabilized driver composed of a feedback amplifier with compensation. The voltage limiter’s features include generating a PMOS-VT difference, being capable of voltage tuning with fuse trimming, and compensation in the driver circuit through zero insertion. It provides a voltage insusceptible to supply-voltage and substrate-voltage bouncings, temperature variation, and process fluctuation, while ensuring the feedback-loop stability with a phase margin of 55° for a time-dependent load of DRAM circuit. The proposed circuits are experimentally evaluated through their implementation in a 16-Mb CMOS DRAM. A temperature dependency of 1.4 mV/°C and a voltage deviation within ± 10% for process fluctuation are achieved. The voltage is stabilized within ±3% for Vcc bounce and ± 10% for memory operation. © 1990 IEEE