9-PS GATE DELAY JOSEPHSON OR GATE WITH MODIFIED VARIABLE THRESHOLD LOGIC

被引：14

作者：

FUJIMAKI, N

KOTANI, S

HASUO, S

YAMAOKA, T

机构：

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS | 1985年 / 24卷 / 01期

关键词：

D O I：

10.1143/JJAP.24.L1

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

引用

页码：L1 / L2

页数：2

共 8 条

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[6]

NAKANO J, 1984, 16TH INT C SOL STAT, P635

[7] LOGIC DELAYS OF 5-MU-M CURRENT-SWITCHED JOSEPHSON GATES [J].

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APPLIED PHYSICS LETTERS, 1982, 40 (08) :739-741

[8] LOGIC DELAYS OF 5-MU-M RESISTOR COUPLED JOSEPHSON LOGIC [J].

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APPLIED PHYSICS LETTERS, 1982, 41 (09) :886-888

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