PAID: Process Aware Imprecise DCT Architecture Trading Quality for Energy Efficiency

With the rapidly increasing usability of multimedia services on portable devices, ultra high energyefficiency has become an imperative requirement for the portable multimedia devices. Most of these devices employ power-devouring compute-intensive units such as Discrete Cosine Transform (DCT) that limit their performance. In addition, as the device dimensions are moving toward sub-nanometer region, process variation (PV) is becoming a major challenge to the VLSI designer. This paper addresses both the problems simultaneously by proposing a novel process aware imprecise DCT (PAID) architecture that exploits relative significance existing in the input and output data. In the PAID architecture, significant computing paths are designed with less delay compared to the nonsignificant paths to reduce the effect of PV. An on-chip PV detector is embedded to reduce the severity of PV for significant sub-blocks only. The energy scalability in PAID architecture is achieved by exploiting the concept of boundary error resiliency. The proposed PAID architecture is evaluated for various benchmark images using different quality metrics. The design is synthesized using 45 nm technology and extracted the Spice netlist. The simulation results show that under severe PV (100% delay variation), PAID computes significant coefficients accurately, thus avoiding severe quality degradation. The proposed PAID architecture provides 32.1% less energy-consumption at the cost of 3.05 dB reduced PSNR in accurate mode over the best-known DCT architecture and provides 56% area reduction over the conventional design.