NUMERICAL-ANALYSIS OF A TRENCH VDMOST STRUCTURE WITH NO QUASI-SATURATION

This paper presents a modification to the conventional VDMOS transistor which considerably reduces the effect of quasi-saturation. This modification consists of introducing a deep trench into the structure which is located in the centre of each MOS cell. By extending the gate oxide and metalization into the trench, an accumulation layer is formed deep into the bulk of the device, which modulates the total drift region resistance. A two-dimensional numerical simulator is used to investigate the electrical and thermal performance of the device through which it is shown that the device not only removes the quasi-saturation effect, but also gives lower on-resistance, and much more attractive synchronous rectifying characteristics when compared to the conventional VDMOST structure with an equivalent geometry.