TEST-GENERATION FOR SEQUENTIAL-CIRCUITS USING PARALLEL FAULT SIMULATION WITH RANDOM INPUTS

被引：0

作者：

TAKAMATSU, Y ^{[1
]}

HIGASHI, I ^{[1
]}

KODAMA, T ^{[1
]}

机构：

[1] FUJITSU LTD,KAWASAKI 221,JAPAN

来源：

SYSTEMS AND COMPUTERS IN JAPAN | 1995年 / 26卷 / 10期

关键词：

SEQUENTIAL CIRCUIT; TEST SEQUENCE; TEST GENERATION; PARALLEL FAULT SIMULATION; STATE CONTROL;

D O I：

10.1002/scj.4690261003

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a simple test generation method for sequential circuits using a parallel simulator with random inputs. The proposed test generation method generates sequences by simulating as many states as possible, without using a cost function for a target fault. To generate effective test sequences, dynamic switching is done between I-Mode and S-Mode parallel simulators. Here the I-Mode simulates 32 patterns for one state in parallel and the S-Mode simulates 32 patterns for 32 states in parallel. Experimental results for ISCAS'89 benchmark sequential circuits show that our method achieves test sequences with high coverage in acceptable CPU time.

引用

页码：24 / 34

页数：11

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