PARAMETERIZED SPICE SUBCIRCUITS FOR MULTILEVEL INTERCONNECT MODELING AND SIMULATION

被引：13

作者：

CHANG, KJ ^{[1
]}

CHANG, NH ^{[1
]}

OH, SY ^{[1
]}

LEE, KY ^{[1
]}

机构：

[1] HEWLETT PACKARD CO,HEWLETT PACKARD LABS,PALO ALTO,CA 94304

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1992年 / 39卷 / 11期

关键词：

D O I：

10.1109/82.204126

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators. As a result, interconnect parasitics are parameterized in a manner similar to the parameterization of transistors in SPICE. Therefore, the effort and time needed by circuit designers or EDA tools to prepare distributed multiline R, C SPICE decks for circuit simulations is drastically reduced.

引用

页码：779 / 789

页数：11

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