COMPLETE TEST-GENERATION METHOD FOR ALL STUCK-AT FAULTS IN COMBINATIONAL-CIRCUITS

被引：0

作者：

GURAN, H

HALICI, U

机构：

[1] Middle East Technical University, Electrical and Electronics Engineering Department, Balgat, Ankara

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS | 1990年 / 68卷 / 05期

关键词：

D O I：

10.1080/00207219008921209

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In combinational logic circuits the generation of complete fault detection test sets requires the determination of the complete test sets of all possible stuck-at faults. In this study, an efficient procedure is developed for finding all the complete test sets of all possible single stuck-at faults in a combinational circuit. The developed procedure primarily uses the properties of logic gates. An example is solved by the use of the developed procedure. © 1990 Taylor and Francis Ltd.

引用

页码：657 / 666

页数：10

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