A 3.8-NS CMOS 16X16-B MULTIPLIER USING COMPLEMENTARY PASS-TRANSISTOR LOGIC

被引：229

作者：

YANO, K ^{[1
]}

YAMANAKA, T ^{[1
]}

NISHIDA, T ^{[1
]}

SAITO, M ^{[1
]}

SHIMOHIGASHI, K ^{[1
]}

SHIMIZU, A ^{[1
]}

机构：

[1] HITACHI VLSI ENGN CORP LTD,TOKYO,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 02期

关键词：

D O I：

10.1109/4.52161

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 3.8-ns 257-mW CMOS 16x16-b multiplier with a supply voltage of 4 V is described. A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as conventional CMOS due to lower input capacitance and higher logic functionality. Its multiplication time is the fastest ever reported, including bipolar and GaAs IC’s, and it can be enhanced further to 2.6 ns with 60 mW at 77 K. 0018-9200/90/0400-0388$01.00 © 1990 IEEE

引用

页码：388 / 395

页数：8

共 11 条

[1] A COMPARISON OF CMOS CIRCUIT TECHNIQUES - DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC VERSUS CONVENTIONAL LOGIC [J].

CHU, KM ;

PULFREY, DL .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (04) :528-532

[2]

HANAMURA S, 1983 S VLSI TECH, P46

[3]

Heller L.G., 1984, ISSCC, P16

[4]

KAJII K, 1987 2EEE CUST INT C, P199

[5]

KENGAKU T, 1987, IECE JAPAN, P2

[6]

OOWAKI Y, 1987, ISSCC DIG TECH PAPER, P52

[7]

PFENNINGS LCM, 1985, ISSCC DIG TECH PAPER, P212

[8]

SASAKI K, 1989, ISSCC DIG TECH PAPER, P34

[9]

SUZUKI M, 1988, ISSCC DIG TECH PAPER, P70

[10]

UYA M, 1984, ISSCC, P90

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