Integration of sol-gel PZT with silicon-on-sapphire CMOS circuitry

被引：5

作者：

Bland, T

Obhi, J

Patel, A

Kirby, P

Robinson, M

Kerr, J

机构：

[1] GEC-Marconi Materials Technology Caswell, Towcester

来源：

MICROELECTRONIC ENGINEERING | 1995年 / 29卷 / 1-4期

关键词：

D O I：

10.1016/0167-9317(95)00109-3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Deposition and patterning processes to produce 9x9 mu m ferroelectric capacitor (FECAP) structures, and the back-end processes necessary to integrate them with silicon-on-sapphire (SOS) circuits have been developed with the aim of demonstrating a 4kbit non-volatile RAM (NVRAM) on SOS. PZT thin film deposition by a sol-gel route has been characterised and dielectric, ferroelectric and fatigue measurements taken.

引用

页码：29 / 32

页数：4