A MODEL FOR DIGITAL PHASE-LOCKED LOOPS AT LOW SNR

被引:0
|
作者
BENTAYEB, S [1 ]
MARAL, G [1 ]
机构
[1] ECOLE NATL SUPER TELECOMMUN,F-31028 TOULOUSE,FRANCE
来源
ANNALES DES TELECOMMUNICATIONS-ANNALS OF TELECOMMUNICATIONS | 1986年 / 41卷 / 3-4期
关键词
D O I
暂无
中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
引用
收藏
页码:133 / 146
页数:14
相关论文
共 50 条
  • [1] Digital Phase-Locked Loops
    Levantino, Salvatore
    2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2018,
  • [2] DIGITAL PHASE-LOCKED LOOPS
    不详
    HEWLETT-PACKARD JOURNAL, 1987, 38 (10): : 15 - 15
  • [3] A Digital BIST for Phase-Locked Loops
    Sliech, Kevin
    Margala, Martin
    23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2008, : 134 - 142
  • [4] Advanced Digital Phase-Locked Loops
    Levantino, Salvatore
    2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2013,
  • [5] ON OPTIMUM DIGITAL PHASE-LOCKED LOOPS
    GUPTA, SC
    IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1968, CO16 (02): : 340 - &
  • [6] Chimeras in digital phase-locked loops
    Paul, Bishwajit
    Banerjee, Tanmoy
    CHAOS, 2019, 29 (01)
  • [7] OPTIMUM DIGITAL PHASE-LOCKED LOOPS
    RUDDELL, AJ
    ROSIE, AM
    ELECTRONICS LETTERS, 1975, 11 (18) : 440 - 441
  • [8] A SURVEY OF DIGITAL PHASE-LOCKED LOOPS
    LINDSEY, WC
    CHIE, CM
    PROCEEDINGS OF THE IEEE, 1981, 69 (04) : 410 - 431
  • [9] Model for Digital Phase-Locked Loops at Low Signal-to-Noise Ratio.
    Bentayeb, Salah
    Maral, Gerard
    1600, (41): : 3 - 4
  • [10] Smoothing the Way for Digital Phase-Locked Loops
    Ho, Cheng-Ru
    Chen, Mike Shuo-Wei
    IEEE MICROWAVE MAGAZINE, 2019, 20 (05) : 80 - 97