MOSFET THRESHOLD EXTRACTION CIRCUIT

被引：10

作者：

MANARESI, N

FRANCHI, E

GNUDI, A

BACCARANI, G

机构：

[1] DEIS, Universitá di Bologna, BO, Viale Risorgimento 2

来源：

ELECTRONICS LETTERS | 1995年 / 31卷 / 17期

关键词：

ANALOG INTEGRATED CIRCUITS; MOSFETS; SEMICONDUCTOR DEVICE CHARACTERIZATION;

D O I：

10.1049/el:19950990

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel method for the extraction of MOST threshold voltage (V-T) is presented. It is based on a self-biasing loop and it allows an output voltage equal to the V-T of either n-MOS or p-MOS transistors to be obtained without any restriction on the particular type of well.

引用

页码：1434 / 1435

页数：2

共 3 条

[1] AN INPUT-FREE V(T) EXTRACTOR CIRCUIT USING A 2-TRANSISTOR DIFFERENTIAL-AMPLIFIER [J].

JOHNSON, MG .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (06) :704-705

[2] A CMOS 4-QUADRANT ANALOG MULTIPLIER WITH SINGLE-ENDED VOLTAGE OUTPUT AND IMPROVED TEMPERATURE PERFORMANCE [J].

WANG, ZH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (09) :1293-1301

[3] AUTOMATIC VT EXTRACTORS BASED ON AN NXN2 MOS-TRANSISTOR ARRAY AND THEIR APPLICATION [J].

WANG, ZH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (09) :1277-1285

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