A HIGH-SPEED CMOS COMPARATOR WITH 8-B RESOLUTION

This paper introduces a high-speed CMOS comparator. The comparator consists of a differential input stage, two regenerative flip-flops, and an S-R latch. No offset cancellation is exploited, which reduces the power consumption as well as the die area and increases the comparison speed. An experimental version of the comparator has been integrated in a standard double-poly double-metal 1.5-mu-m n-well process with a die area of only 140 x 100-mu-m2 . This circuit, operating under a +2.5/-2.5-V power supply, performs comparison to a precision of 8 b with a symmetrical input dynamic range of 2.5 V (therefore +/- 0.5 LSB resolution is equal to +/- 4.9 mV).