Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

被引：34

作者：

Kwong, D. -L. ^{[1
]}

Li, X. ^{[1
,2
]}

Sun, Y. ^{[1
,2
]}

Ramanathan, G. ^{[1
,2
]}

Chen, Z. X. ^{[1
]}

Wong, S. M. ^{[1
,2
]}

Li, Y. ^{[1
,3
]}

Shen, N. S. ^{[1
]}

Buddharaju, K. ^{[1
]}

Yu, Y. H. ^{[1
,2
]}

Lee, S. J. ^{[1
,3
]}

Singh, N. ^{[1
]}

Lo, G. Q. ^{[1
]}

机构：

[1] ASTAR, Inst Microelect, 11 Sci Pk Rd, Singapore 117685, Singapore

[2] Nanyang Technol Univ, Dept Elect & Elect Engn, Singapore 639798, Singapore

[3] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore 117576, Singapore

来源：

JOURNAL OF NANOTECHNOLOGY | 2012年 / 2012卷

关键词：

D O I：

10.1155/2012/492121

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.

引用

页数：21

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