共 50 条
- [22] Simulation of CTCS-3 Protocol with Temporal Logic Programming PROCEEDINGS OF THE 2013 IEEE 17TH INTERNATIONAL CONFERENCE ON COMPUTER SUPPORTED COOPERATIVE WORK IN DESIGN (CSCWD), 2013, : 72 - 77
- [23] How to Use Temporal Logic in Combinational Circuits Verification with SMV INFORMATICS 2013: PROCEEDINGS OF THE TWELFTH INTERNATIONAL CONFERENCE ON INFORMATICS, 2013, : 83 - 87
- [26] ESTL: A temporal logic for events and states APPLICATION AND THEORY OF PETRI NETS 1998, 1998, 1420 : 365 - 384
- [29] Temporal logic in verification of digital circuits JOURNAL OF ELECTRICAL ENGINEERING-ELEKTROTECHNICKY CASOPIS, 2008, 59 (01): : 14 - 22