EXPERIMENTAL IMPLEMENTATION OF ANALOG-TO-DIGITAL CONVERTER BASED ON THE REVERSIBLE RIPPLE COUNTER

A new A/D converter which includes a comparator, reversible binary counter with DC outputs has been designed, fabricated and tested. The comparator generates two trains of the SFQ pulses in response to increasing or decreasing of the input signal. The pulses are transferred through SFQ transmission lines to the adding and diminishing inputs of a reversible counter. The reversible counter has been realized by supplementing to the usual counter the SFQ transmission lines, splitters, and confluence elements for sending diminish pulses directly to each bit. Non-destructive read-out of the counter contents is carried out by SFQ/DC converters connected to each counter bit. The integrated circuit is fabricated using 5 mu-m Nb-AlOx-Nb Josephson-junction technology with critical current density about 500 A/cm2. External Mo shunts of the junctions provide the value of beta-(c) less-than-or-equal-to 1 and I(c)R almost-equal-to 300 mu-V. The A/D conversion is studied for low frequency signals with an external clock. High-frequency performance of the reversible counter has been tested by observation of frequency scaling down.