Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits

被引：0
作者：
L.-R. Zheng
H. Tenhunen
机构：
[1] Royal Institute of Technology,Department of Electronics, Electronic System Design Laboratory
来源：
Analog Integrated Circuits and Signal Processing | 2002年 / 30卷
关键词：
power distribution; signal integrity; deep submicron CMOS; system-on-chip;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper proposes a new design methodology and new models for power integrity analysis in deep submicron system-on-chip circuit design. The placement plan and interconnect plan are the first design steps, preceding a priori signal and power integrity estimations. The initial power distribution is refined progressively from early mode to final placement and layout. In order to improve accuracy and efficiency in early stage estimates, a multilevel dynamic interconnect model and a fast power distribution model are employed, which consequently result in a drastic reduction of the number of iterations through the design cycle. HSPICE simulations verify the efficiency and the accuracy of the method. Finally, some noise-reduced power distribution techniques such as self-decoupling and area array power/ground pin distribution are discussed, and measurement result for effective power distribution is presented.
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页码：15 / 29
页数：14
相关论文
共 27 条
  • [1] Restle P. J.(1998)Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor IEEE Journal of Solid-State Circuits 33 662-665
  • [2] Jenkins K. A.(2000)Interconnect modeling in deep-submicron design IEICE Trans. Electron. E83-c 1311-1316
  • [3] Deutsch A.(1998)Interconnect and circuit modeling techniques for full-chip power supply noise analysis IEEE Trans. Comp., Packag., Manufact. Technol. B 21 209-215
  • [4] Cook P. W.(1998)Interconnect and substrate modeling and analysis: an overview IEEE Journal of Solid-State Circuits 33 1445-1452
  • [5] Jung W. Y.(1998)A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation IEEE Journal of Solid-State Circuits 33 657-661
  • [6] Oh S. Y.(1992)Multilevel metal capacitance models for CAD design synthesis systems IEEE Electron Device Lett. 13 32-34
  • [7] Kong J. T.(1983)Simple formulas for two-and three-dimensional capacitance IEEE Trans. Electron Devices ED-30 183-185
  • [8] Lee K. H.(1984)An analysis of interconnect line capacitance and coupling for VLSI circuits Solid-State Electron. 27 742-749
  • [9] Chen H. H.(1999)Early timing closure for deep sub-micron design Electronic Engineering 71 47-49
  • [10] Neely J. S.(1991)Simultaneous switching ground noise calculation for packaged CMOS devices IEEE Journal of Solid-State Circuits 26 1724-1728
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