VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

In this paper, hardware efficient truncated multiplier using modified booth algorithm is proposed for signed bit multiplication, such that the average absolute error is kept minimum. The proposed methodology truncates the least significant bits (LSBs) of the final product and thus minimizes the number of full adders and half adders used in partial product accumulation. This we achieve by non-generation of an initial partial product and deletion of certain LSBs in higher order partial products. To minimize the error due to non generation and omission, we add compensation bits at appropriate retained bit positions. Experimental analysis of the proposed truncation algorithm implemented in modified booth encoded multiplier using Synopsys design compiler demonstrates area saving of nearly 25.1 % for an 8 × 8 design. The functionality of the proposed design is verified by implementing in a signal processing system.