High speed RLC equivalent RC delay model for global VLSI interconnects

Current-mode signaling significantly is known for increasing the bandwidth of on-chip interconnects and reduces the overall propagation delay. In this paper feature of current mode interconnects is exploited for investigating the performance of RLC equivalent ReffCT mathematical delay model of interconnects. This is due to a simple RC interconnects model which results a significant error in delay estimation. Due to this equivalency the non ideal effect of inductive behavior at high frequencies and scaled technologies can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. The performance of delay model is further estimated for voltage and current mode interconnects. When test results are estimated with voltage and current mode systems, it is observed that the equivalent model is superior to the traditional Elmore and Sakurai delay model.