V-band CMOS injection-locked frequency tripler using differential harmonic current injection technique

This letter presents a V-band CMOS injection-locked frequency tripler (ILFT) fabricated in a standard 90-nm CMOS process. By employing a differential harmonic current injection technique, a frequency doubler (2f0) realized in the connected source terminal of injection transistors is to mix with injection signals (f0) through injection transistors, and output signals (3f0 = 2f0 + f0) are obtained from output buffers. The proposed ILFT improves the locking range and power dissipation by adopting two cross-coupled transistor pairs, and strengthens the rejection ability of second-order harmonic by using a resonator network. The proposed ILFT has the free-running frequency of 62.49 GHz and locking ranges of 61.2 to 64.2 GHz as input injection signals from 20.4 to 21.4 GHz at an input power level of 0 dBm. The proposed ILFT core consumes 7.48 mW from a supply voltage of 1.1 V.