A fast locked and low phase noise all-digital phase locked loop based on model predictive control

An all-digital phase locked loop (ADPLL) taking new approach for design of the loop filter is presented. A feedback loop in the time domain by modeling the DCO and TDC as an appropriate model in the state-space form is proposed. Then, a model predictive control (MPC) method for designing loop filter in order to generate an optimal control signal is employed. The proposed loop filter can overcome latency issue that inevitably exists in most of digital systems. Furthermore, the proposed MPC loop filter achieves rapid transient response time and enables us to model other noise sources resulted from oscillator pulling and flicker noise which are common problems in many modern transceivers and the effects of which can be dramatically removed without degrading the overall phase noise performance. Simulation results confirm the capability of the proposed design and show it is significantly more robustness against these problems compared to conventional digital PLL.