Total ionizing dose effects in junctionless accumulation mode MOSFET

被引:0
作者
Avashesh Dubey
Rakhi Narang
Manoj Saxena
Mridula Gupta
机构
[1] University of Delhi South Campus,Semiconductor Device Research Laboratory, Department of Electronic Science
[2] University of Delhi,Department of Electronics, Sri Venkateswara College
[3] University of Delhi,Department of Electronics, Deen Dayal Upadhyaya College
来源
Applied Physics A | 2021年 / 127卷
关键词
Junctionless accumulation mode MOSFET; Gamma radiation; Total ionizing dose (TID); Border traps; Low-frequency noise; Sentaurus TCAD; Dosimeter; Radiation reliability;
D O I
暂无
中图分类号
学科分类号
摘要
In this paper, an extensive investigation of low-frequency (1/f) noise and total ionizing dose–response of junctionless accumulation mode double-gate (JAM DG) MOSFET is presented. Current–voltage (Id–Vg) characteristics and low-frequency noise of JAM DG MOSFET are simulated at different ionized doses and compared to different gate oxide thickness and different channel doping concentrations. A significant amount of irradiation-induced threshold voltage shift and increase in low-frequency noise is observed for different gate oxide thickness and channel doping concentration. Moreover, the irradiation-induced border trap densities are also obtained at different doses. The gamma radiation model of Sentaurus TCAD is used to get the required results.
引用
收藏
相关论文
共 270 条
[1]  
Frank D(2001)Device scaling limits of Si MOSFETs and their application dependencies Proc. IEEE 89 259-288
[2]  
Dennard R(2008)Scaling of nanowire transistors IEEE Trans. Electron Devices 55 2846-2858
[3]  
Nowak E(2008)A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate IEEE Electron Device Lett. 29 718-720
[4]  
Solomon P(2008)Multiple-gate CMOS thin-film transistor with polysilicon nanowire IEEE Electron Device Lett. 29 102-105
[5]  
Taur Y(2011)Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors Nature 479 310-316
[6]  
Wong H(2000)FinFET—A self-aligned double-gate MOSFET scalable to 20 nm IEEE Trans. Electron Devices 47 2320-2325
[7]  
Yu B(2006)High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices IEEE Electron Device Lett. 27 383-385
[8]  
Yuan Y(2009)Colinge, junctionless multigate field-effect transistor Appl. Phys. Lett. 94 53511-229
[9]  
Asbeck PM(2010)Nanowire transistors without junctions Nat. Nanotechnol. 5 225-103
[10]  
Taur Y(2010)Performance estimation of junctionless multigate transistors Solid State Electron 54 97-1481