Structural models of finite-state machines for their implementation on programmable logic devices and systems on chip

Digital systems based on programmable logic devices and systems on chip often use register buffers for the transmission of signals between functional units. In this paper, structural models of finite state machines (FSMs) that allow the use of input and output buffer triggers as memory elements of the finite state machine are considered. To this end, a new classification of structural models of finite state machines is proposed in which all finite state machines are divided into six classes A, B, C, D, E, and F. In the models C and D, output buffer triggers are used as memory elements; in the models E and F, input buffer triggers are used for this purpose. A definition of the set of internal states of FSMs in each class is given and synthesis methods for the FSMs of the classes C-F are proposed. The results of experiments showed that the use of FSM models of the classes C-F reduces the number of internal memory elements by 2.22% to 25.83% on the average and sometimes even by 100%.