A low-complexity MPEG-2 to H.264/AVC wavefront intra-frame transcoder architecture

We present a reconfigurable high-throughput MPEG-2 to H.264/AVC intra-frame transcoding architecture with wavefront data processing. The proposed FPGA implementation deals with the highly data-dependent critical path of the transcoder, and with low-complexity synchronization of the encoding and decoding stages. Furthermore, the implementation is applicable for reconfiguration and limits the communication bandwidth to the surrounding system through use of on-chip memory. The computationally demanding units of the MPEG-2 decoder have been implemented by processing 8 pixels in parallel, whereas H.264/AVC encoder engine utilizes a 4 × 4 block-level pipeline. The synchronous communication between the stages and full pipeline of the system is achieved by an intermediate memory buffer mechanism. A wavefront macroblock level scanning order based on the on-the-fly processing of consecutive macroblocks and on-chip memory organization are proposed. Achieved results represent a significant reduction of minimal required frequency compared to the state of the art for resolutions CIF, SD and HD1080p. Furthermore, the proposed transcoding core with encoder stage in full pipeline has maximal throughput of 1744 Mpixels/s that corresponds to processing of UHD 4320p resolution at 30 fps.