Effect of epilayer characteristics and processing conditions on the thermally oxidized SiO2/SiC interface

The optimization of the SiO2/SiC interface is critical for the development of SiC MOS devices. We investigate the effects of several variables spanning both epilayer attributes and processing conditions relative to our control oxidation process. Varying the shallow vicinal angle of the wafer does not affect the interface. There is a definite degradation of the interface as the epilayer doping density is increased. Sacrificial oxidation appears to reduce the number of border traps in the final oxide. Fluorine annealing has no effect on the interface quality. A low temperature (950°C) re-oxidation, which follows a bulk oxide growth at 1150°C, reduces Dit to the mid-1010 cm−2eV−1 range near midgap and Qf to a reacord low 5×1011 cm−2.