Low-power tri-state buffer in MOS current mode logic

被引:0
作者
Kirti Gupta
Neeta Pandey
Maneesha Gupta
机构
[1] Delhi Technological University,Department of Electronics and Communication Engineering
[2] Netaji Subhas Institute of Technology,Department of Electronics and Communication Engineering
来源
Analog Integrated Circuits and Signal Processing | 2013年 / 75卷
关键词
MOS current mode logic; Tri-state buffer; Low power; Differential;
D O I
暂无
中图分类号
学科分类号
摘要
In this paper, a low-power tri-state buffer in MOS current mode logic (MCML) is proposed. It offers power saving by reducing the overall current flow in the circuit during the high-impedance state. The proposed MCML tri-state buffer is simulated in PSPICE using 0.18 μm TSMC CMOS technology parameters. Its performance comparison with the existing MCML tri-state buffers indicates that the proposed tri-state buffer is power efficient than the others.
引用
收藏
页码:157 / 160
页数:3
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