Compact and Broadband Variable True-Time Delay Line with DLL-Based Delay-Time Control

This study presents the design and implementation of a compact and wideband active variable true-time delay line for timed array applications. Using a combination of coarse delay cells and fine delay cells, the proposed delay line achieves a large delay range and a high delay tuning resolution. Instead of LC delay lines or transmission lines, the delay can be approximated by compact active filters using transconductors and capacitors. The coarse delay cell adopts inductive peaking to broaden the bandwidth, and the fine delay cell employs a novel differential active inductor to improve the delay resolution and integration level. The group delays of the coarse delay cells and fine delay cells are analyzed and optimized. The signal transmission path is controlled by path-selection amplifiers and V–I conversion switches to achieve delay variability. The delay time is calibrated by the delay-locked loop (DLL) to mitigate the process, voltage and temperature variations. The complementary metal-oxide-semiconductor (CMOS) variable true-time delay line is fabricated in a 0.18-μm\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu \hbox {m}$$\end{document} CMOS process. Experiments indicate that the maximal relative delay is 95 ps and that the delay resolution is 5 ps within a 10% delay variation over a frequency range of 0.6–4.2 GHz. The chip dissipates 88 mW under a 1.8-V supply, and the core area including the DLL circuit is only 0.05 mm2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\hbox { mm}^{2}$$\end{document}.