Spice modeling of oxide and interface trapped charge effects in fully-depleted double-gate FinFETs

As is the case with conventional planar MOS transistors, the electrical characteristics of highly-scaled multi-gate field-effect transistors (FinFETs) also suffer from temporal degradations occurring due to hot-carrier injection, bias temperature instability and/or ionizing-radiation damage. The FinFETs aging is caused by cumulative contribution of the generation of oxide/Si interface traps and positively charged defects within the gate oxide. The accurate capturing of the dynamic contribution of the both trapped charges by the FinFET electrical models in Spice simulations is important for lifetime prediction and verification of long-term performance of advanced CMOS ICs. In this paper, the auxiliary sub-circuit is described aimed for including the effects of oxide and interface trapped charges in Spice electrical models of fully-depleted double-gate FinFETs. The efficiency of the proposed sub-circuit for modeling the aging effects in double-gate FinFETs is verified using two-dimensional TCAD device simulations.