A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs

被引：0
作者：
F. Azaïs
S. Bernard
Y. Bertrand
M. Renovell
机构：
[1] Université de Montpellier II: Sciences et Techniques du Languedoc,Laboratoire d'Informatique Robotique Microélectronique de Montpellier (LIRMM)
来源：
Journal of Electronic Testing | 2001年 / 17卷
关键词：
analog and mixed-signal testing; ADC test; Built-In Self-Test (BIST);
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.
引用
收藏
页码：139 / 147
页数：8
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