Low-Power Constant-Coefficient Multiplier Generator

被引：0
|
作者：
Cheng-Yu Pai
A.J. Al-Khalili
W.E. Lynch
机构：
[1] Concordia University,Department of Electrical and Computer Engineering
来源：
Journal of VLSI signal processing systems for signal, image and video technology | 2003年 / 35卷
关键词：
constant multipliers; design automation; VHDL; DSP; integer multiplication; low power;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Constant-coefficient multipliers are used in many DSP cores. A new low-power constant multiplier, with detailed design procedure, is presented. By using canonical sign-digit (CSD) number system, and introducing new simplification techniques and identities, the multiplier features a new algorithm to reduce logic depth for the Wallace-tree implementation. The method also reduces area and complexity.
引用
收藏
页码：187 / 194
页数：7
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