An ultra low die area 8-b ADC and its generic calibration logic

被引:0
作者
Nikos Petrellis
Michael Birbas
机构
[1] Analogies S.A.,
[2] Technological Educational Institute of Larisa,undefined
来源
Analog Integrated Circuits and Signal Processing | 2012年 / 70卷
关键词
A/D conversion; Calibration; Low area; Low power; Subrange architecture; Integer division;
D O I
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中图分类号
学科分类号
摘要
The 8-bit voltage mode subrange A/D converter described in this paper operates in a mid-input signal frequency range of up to 20 MHz and requires at least an order of magnitude lower die area (0.06 mm2) than other A/D converters with a similar resolution. Moreover, it dissipates only 4.5 mW power and is supported by a calibration logic that is general enough to be used by several other measurement and instrumentation applications that require a real time adjustment of the amplitude and the level of their differential signals. This voltage mode subrange A/D converter architecture is actually an asynchronous two-step A/D converter that is based on a novel integer division operation. The current mode implementation of such an integer divider has already been employed by the authors in an innovative low area/power binary tree A/D conversion architecture. The voltage mode implementation of the integer divider allows the realization of the higher speed and lower power/area subrange A/D converter that is presented in this article.
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页码:323 / 335
页数:12
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