Fabrication and Simulation of InGaAs Field-Effect Transistors with II–VI Tunneling Insulators

被引:0
|
作者
E. Suarez
P.-Y. Chan
M. Gogna
J.E. Ayers
E. Heller
F. Jain
机构
[1] Department of Electrical,ECE Department
[2] Computer,undefined
[3] and Energy Engineering,undefined
[4] ,undefined
[5] University of Connecticut,undefined
[6] Synopsys Inc.,undefined
来源
关键词
InGaAs; nonvolatile memory FETs; FET simulation; MOCVD fabrication; three-state;
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学科分类号
摘要
This study shows the use of a high-κ ZnS/ZnMgS/ZnS heteroepitaxial tunneling layer in an InGaAs field-effect transistor. Experimental fabrication and simulation of this semiconductor structure show promise of reducing threshold voltage variation by replacing silicon and hafnium oxides as a gate insulator. The II–VI tunneling insulator is grown on an InGaAs substrate using ultraviolet-irradiated metalorganic vapor-phase epitaxy. GeOx-Ge cladded quantum dots are self-assembled to form the gate material. The gate consists of two self-assembled individually cladded quantum dot layers which allow multilogic behavior. Simulations calculated by solving the Schrödinger and Poisson equations self-consistently confirm experimental ID–VD characteristics and show the electron distribution in an inversion channel/quantum well under different gate voltage bias values.
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页码:3064 / 3068
页数:4
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