Architecture design of low-power motion estimation based on DHS-NPDS for H.264/AVC

被引：0
作者：
YunBi Chen
ZhengDong Li
Li Guo
JinSheng Xie
Long Zhao
机构：
[1] University of Science and Technology of China,Department of Electronic Science and Technology
[2] Chongqing Communication College,Staff room of Electronic and Technology
来源：
Science China Information Sciences | 2012年 / 55卷
关键词：
partial distortion search; adaptive search range; low-power; low-bandwidth; pipeline; VLSI;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A novel architecture of motion estimation (ME) based on improved normalized partial distortion search is proposed to meet three primary requirements for real-time video encoding, which are low-power, low-bandwidth and high area utilization efficiency. The ME engine supports both normalized partial distortion search and adaptive search window adjustment. The former can reduce the computational complexity of ME to save power and area; the latter can avoid unnecessary accessing the external memory to lower the data bandwidth. The proposed engine has been implemented with UMC 90nm CMOS technology. The implementation results show that, compared with traditional engines, the engine can achieve significant improvements of the hardware efficiency and the power efficiency respectively with a little throughput compromise.
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页码：2234 / 2242
页数：8
相关论文
共 33 条
[1]  
Chen T. C.(2006)Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder IEEE Trans Circ Syst Vid 16 673-688
[2]  
Chien S. Y.(2007)Improved normalized partial distortion search with dual-halfway-stop for rapid block motion estimation IEEE Trans Multimedia 9 995-1003
[3]  
Huang Y. W.(1998)A low-power VLSI architecture for full-search block-matching motion estimation IEEE Trans Circ Syst Vid 8 393-398
[4]  
Yi X. Q.(2006)Low-power systolic array processor architecture for FSBM video motion estimation Electron Lett 42 1146-1147
[5]  
Ling N.(2010)A dynamic search range algorithm for stabilized reduction of memory traffic in video encoder IEEE Trans Circ Syst Vid 20 1041-1046
[6]  
Do V. L.(2002)On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture IEEE Trans Circ Syst Vid 12 61-72
[7]  
Yun K. Y.(2011)An efficient parallel architecture for one-bit transform based motion estimation J Electron Inform Technol 33 717-722
[8]  
Jiang M.(2008)A high-performance reconfigurable VLSI architecture for VBSME in H.264 IEEE Trans Consum Electr 54 1338-1345
[9]  
Crookes D.(2004)A VLSI architecture for variable block size video motion estimation IEEE Trans Circuits II 51 384-389
[10]  
Davidson S.(2005)An efficient VLSI architecture for H.264 variable block size motion estimation IEEE Trans Consum Electr 51 1291-1299
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