Phase Detectors/Phase Frequency Detectors for High Performance PLLs

被引:0
作者
Hiroyasu Yoshizawa
Kenji Taniguchi
Kenichi Nakashi
机构
[1] Kyushu University,Department of Electronics, Graduate School of Information Science and Electrical Engineering
[2] Kurume Institute of Technology,Department of Electronics and Information Engineering
[3] Kyushu University,Department of Electrical and Electronic Systems Engineering, Graduate School of Information Science and Electrical Engineering
来源
Analog Integrated Circuits and Signal Processing | 2002年 / 30卷
关键词
PLL; PD; PFD; dynamic CMOS logic; feedforward reset; delay cell with VCO replica;
D O I
暂无
中图分类号
学科分类号
摘要
Phase Frequency Detectors (PFDs) for use in clock distribution PLLs and Phase Detectors (PDs) for clock recovery PLLs that we have proposed recently to achieve high performance are reviewed and discussed. For the PFD, operating speed limitation and phase detecting characteristics are improved with two kinds of approaches, i.e., gate/logic design and configuration design. For the PD, a simple compensation technique to prevent the deterioration of the phase detecting characteristics by D-F/F and a new PD with delay cell of VCO replica are proposed to reduce the jitter caused by PD. By SPICE simulations and experiments, it is confirmed that the maximum operating speed of PFD is improved to more than twice of conventional one and the jitter caused by PD is reduced to a minimum level.
引用
收藏
页码:217 / 226
页数:9
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