DivSIM , an interactive simulator for LLVM bitcode

被引:0
作者
Petr Ročkai
Jiří Barnat
机构
[1] Masaryk University,Faculty of Informatics
来源
International Journal on Software Tools for Technology Transfer | 2022年 / 24卷
关键词
Simulation; Model checking; Counterexample; Parallelism; Abstract interpretation; Symbolic execution; LLVM;
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学科分类号
摘要
In this paper, we introduce an interactive simulator for programs in the form of LLVM bitcode. The main features of the simulator include precise control over thread scheduling, automatic checkpoints and reverse stepping, support for source-level information about functions and variables in C and C++ programs and structured heap visualisation. Additionally, DivSIM is compatible with DiVM (DIVINE VM) hypercalls, which makes it possible to load, simulate and analyse counterexamples from an existing model checker, and with abstract bitcode generated by LART (LLVM Abstraction and Refinement Tool), making it suitable for direct analysis of abstract and/or symbolic programs and counterexamples.
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页码:493 / 510
页数:17
相关论文
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Abdulla PA(2017)Stateless model checking for TSO and PSO Acta Inform. 54 789-818
[2]  
Aronis S(2018)DiVM: model checking with LLVM and graph memory J. Syst. Softw. 143 1-13
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