Robust and Efficient OFDM Synchronization for FPGA-Based Radios

被引:0
|
作者
Thinh Hung Pham
Ian V. McLoughlin
Suhaib A. Fahmy
机构
[1] Nanyang Technological University,School of Computer Engineering
[2] The University of Science and Technology of China,School of Information Science and Technology
来源
Circuits, Systems, and Signal Processing | 2014年 / 33卷
关键词
OFDM; Synchronization; OFDM Implementation; FPGA; IEEE 802.16; Software defined radio;
D O I
暂无
中图分类号
学科分类号
摘要
Orthogonal frequency division multiplexing (OFDM) is a popular modulation technique that can combat impulsive noise, is robust to multipath fading, is spectrally efficient, and can allow flexible allocation of spectrum. It has become a key standard in cognitive radio systems as well as an enabling technology for mobile data access systems. An OFDM receiver’s performance is heavily impacted by the accuracy of its symbol timing offset (STO) and carrier frequency offset (CFO) estimation. This paper proposes a novel OFDM synchronization method that combines robust performance with computational efficiency. FPGA prototyping is used to explore the trade-off between the number of computations to be performed and computation word length with respect to both synchronization performance and power consumption. Through simulation, the proposed method is shown to provide accurate fractional CFO estimation as well as STO estimation in a range of channels. In particular, it can yield excellent synchronization performance in the face of a CFO that is larger than many state-of-the-art synchronization implementations can handle. The system implementation demonstrates efficient resource usage and reduced power consumption compared with existing methods, and this is explored as a fine-grained trade-off between performance and power consumption. The result is a robust method suitable for use in low-power radios, enabling less precise analog front ends to be used.
引用
收藏
页码:2475 / 2493
页数:18
相关论文
共 50 条
  • [31] FPGA-Based Approximate Multiplier for Efficient Neural Computation
    Zhang, Hao
    Xiao, Hui
    Qu, Haipeng
    Ko, Seok-Bum
    2021 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-ASIA (ICCE-ASIA), 2021,
  • [32] A FPGA-based Design of Efficient QKD Sifting Module
    Li, Qiong
    Lin, Zhibin
    Le, Dan
    Liu, Hucheng
    2014 TENTH INTERNATIONAL CONFERENCE ON INTELLIGENT INFORMATION HIDING AND MULTIMEDIA SIGNAL PROCESSING (IIH-MSP 2014), 2014, : 219 - 222
  • [33] Efficient and accurate FPGA-based simulator for Molecular Dynamics
    Cho, Eunjung
    Bourgeois, Anu G.
    Fernandez-Zepeda, Jose A.
    2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8, 2008, : 3337 - +
  • [34] On efficient implementation of FPGA-based hyperelliptic curve cryptosystems
    Elias, Grace
    Miri, Ali
    Yeap, Tet-Hin
    COMPUTERS & ELECTRICAL ENGINEERING, 2007, 33 (5-6) : 349 - 366
  • [35] An efficient wavelet image encoder for FPGA-based designs
    Lanuzza, M
    Perri, S
    Corsonello, P
    Cocorullo, G
    2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS), 2005, : 652 - 656
  • [36] Area-efficient FPGA-based FFT processor
    Sansaloni, T
    Pérez-Pascual, A
    Valls, J
    ELECTRONICS LETTERS, 2003, 39 (19) : 1369 - 1370
  • [37] A simplified and efficient implementation of FPGA-based turbo decoder
    Sharma, S
    Attri, S
    Chauhan, FC
    2003 IEEE INTERNATIONAL PERFORMANCE, COMPUTING, AND COMMUNICATIONS CONFERENCE PROCEEDINGS, 2003, : 207 - 213
  • [38] An FPGA-Based PID Controller Design for Chaos Synchronization by Evolutionary Programming
    Yau, Her-Terng
    Pu, Yu-Chi
    Li, Simon Cimin
    DISCRETE DYNAMICS IN NATURE AND SOCIETY, 2011, 2011
  • [39] FPGA-Based Testbed for Synchronization on Ethernet Fronthaul with Phase Noise Measurements
    Paulo, Joary
    Freire, Igor
    Sousa, Ilan
    Lu, Chenguang
    Berg, Miguel
    Almeida, Igor
    Klautau, Aldebaro
    2016 1ST SYMPOSIUM ON INSTRUMENTATION SYSTEMS, CIRCUITS AND TRANSDUCERS (INSCIT), 2016, : 132 - 136
  • [40] An Energy-Efficient FPGA-based Matrix Multiplier
    Tan, Yiyu
    Imamura, Toshiyuki
    2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2017, : 514 - 517