Design and Analysis of Low Power FinFET SRAM with Leakage Current Reduction Techniques

This article examines the development of a low power FINFET SRAM and applying different techniques to reduce leakage current. Due to scalability, the CMOS parameters are not providing reliable values at lower technology nodes. Researchers are looking for solutions to mitigate the negative consequences of MOSFET scaling, and FINFET has emerged as one of the best substitutes since it has better control over the gate and provide better performance parameters like it conserves less energy, eliminates short-channel effects, and reduces leakage current at sub-32 nm regime. Since the number of battery-powered portable devices has dramatically increased, electronic devices must be operated for longer time once the battery has charged. To achieve this the device should have less leakage current so that least amount of leakage power is possible which results in devices to operate for long periods of time. At first, a 6-T CMOS SRAM was designed, and all the parameters were calculated. Subsequently, DG-FINFET SRAM was developed, and all the parameters were calculated. The 6 T cell design based on FinFET consumes considerably less power than the 6 T SRAM designed by CMOS. Additionally, it features hold SNM and RSNM are better than the CMOS 6 T cell by 18% and 26% respectively. To reduce leakage current further in the FinFET SRAM many leakages current reduction techniques are applied and evaluated, which results MTCMOS technique reduced leakage current by 21.38%, SVL by 13.15%, AVL by 17.19% and proposed technique by 24.31%, which shows that the proposed technique has less leakage current than all the techniques discussed.