A fractional spur suppression technique in the fractional-N frequency synthesizer

A fractional spur suppression technique is presented based on the principle of spur generation, which makes the phase between the divider output and the reference be permanently coherent like integer-N frequency synthesizer, so a real lock is achieved. The spurious tones are strongly reduced without sacrificing the PLL bandwidth. The detailed scheme and corresponding key building blocks are deeply discussed. A 1.9 GHz frequency synthesizer with a 100 kHz bandwidth is implemented with the proposed way. SpectreVerilog simulation results show that the technique can reduce over 10 dBc/Hz spurious tones. So it is suitable for high spectral purity frequency synthesizer.