Low-voltage arithmetic units based on fully depleted SOI CMOS nanotransistors

被引：0
作者：
Masal'Skii N.V. [1 ]
机构：
[1] Institute of Physics and Technology, Russian Academy of Sciences
来源：
Russian Microelectronics | 2010年 / 39卷 / 1期
关键词：
Delay Time; Threshold Voltage; RUSSIAN Microelectronics; Full Adder; Control Range;
D O I：
10.1134/S1063739710010075
中图分类号：
学科分类号：
摘要：
Approaches to the development of low-voltage low-power-demand arithmetic units on the basis of silicon-on-insulator nanotransistors are considered. The characteristics of physical models of one- and eight-bit adders based on fully depleted silicon-on-insulator complementary metal-oxide-semiconductor nanotransistors with different topological parameters are numerically analyzed. For some selected elements, the dependences of the delay time and switching power on supply voltage below 1 V are studied for different voltages at the back gate of the transistor. © 2010 Pleiades Publishing, Ltd.
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页码：54 / 62
页数：8
相关论文
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