A Distributed Capacitance Analysis of Co-Planar Inductors for a CMOS QVCO with Varactor Tuned Buffer Stage

A quadrature voltage controlled oscillator (QVCO) topology exhibiting low power consumption and high phase noise performance at low supply voltages is presented. The QVCO buffer includes varactors to maximize the output voltage and minimize the current consumption. Microstrip theory and the principle of conservation of energy have been used to evaluate the distributed capacitances of symmetrical inductors to better predict the resonance frequency. The QVCO is implemented in a 0.25 μm CMOS process from Agere Systems. The total current consumption including the buffer is 5.4 mA at 1.3 V supply, where of the QVCO uses 2.0 mA. The phase noise measures below −138 dBc/Hz at 3 MHz offset frequency over the 8.9% tuning range 1.715 GHz– 1.875 GHz.