Quantifying Error in Dynamic Power Estimation of CMOS Circuits

被引:0
|
作者
Puneet Gupta
Andrew B. Kahng
Swamy Muddu
机构
[1] UC San Diego,Department of Electrical and Computer Engineering
[2] UC San Diego,Department of Computer Science and Engineering
来源
Analog Integrated Circuits and Signal Processing | 2005年 / 42卷
关键词
power; crosstalk; coupling;
D O I
暂无
中图分类号
学科分类号
摘要
Conventional power estimation techniques are prone to many sources of error. With increasing dominance of coupling capacitances, capacitive coupling potentially contributes significantly to power consumption in the deep sub-micron regimes. We analyze potential sources of inaccuracy in power estimation, focusing on those due to coupling. Our results suggest that traditional power estimates can be off by as much as 50%.
引用
收藏
页码:253 / 264
页数:11
相关论文
共 50 条
  • [1] Quantifying error in dynamic power estimation of CMOS circuits
    Gupta, P
    Kahng, AB
    4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, : 273 - 278
  • [2] Quantifying error in dynamic power estimation of CMOS circuits
    Gupta, P
    Kahng, AB
    Muddu, S
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2005, 42 (03) : 253 - 264
  • [3] Accurate power estimation for CMOS circuits
    Shiue, WT
    IEEE REGION 10 INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONIC TECHNOLOGY, VOLS 1 AND 2, 2001, : 829 - 833
  • [4] Peak power estimation for CMOS circuits
    Kuang, JS
    Niu, XY
    He, HZ
    Min, YH
    7TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XV, PROCEEDINGS: COMMUNICATION, CONTROL, SIGNAL AND OPTICS, TECHNOLOGIES AND APPLICATIONS, 2003, : 322 - 325
  • [5] Low dynamic power and low leakage power techniques for CMOS motion estimation circuits
    Kobayashi, N
    Ei, T
    Enomoto, T
    IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (03): : 271 - 279
  • [6] Dynamic Power Saving for CMOS Circuits
    Yeap, Kim Ho
    Ng, Len Luet
    Mazlan, Ahmad Uzair
    Loh, Siu Hong
    Tshai, Kim Hoe
    JURNAL KEJURUTERAAN, 2024, 36 (04): : 1399 - 1407
  • [7] An optimization-based error calculation for statistical power estimation of CMOS logic circuits
    Kwak, B
    Park, ES
    1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 690 - 693
  • [8] Logical effort based dynamic power estimation and optimization of static CMOS circuits
    Kabbani, A.
    INTEGRATION-THE VLSI JOURNAL, 2010, 43 (03) : 279 - 288
  • [9] Power estimation and power noise analysis for CMOS circuits
    Deng, AC
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 1997, 7 (01) : 17 - 30
  • [10] Power estimation of CMOS circuits via power software
    Rodnunsky, NL
    Margala, M
    Durdle, NG
    UNIVERSITY AND INDUSTRY - PARTNERS IN SUCCESS, CONFERENCE PROCEEDINGS VOLS 1-2, 1998, : 149 - 152