Modeling and Analysis of a Front High-k gate stack Dual-Material Tri-gate Schottky Barrier Silicon-on-Insulator MOSFET with a Dual-Material Bottom Gate

被引：0
作者：
Pritha Banerjee
Subir Kumar Sarkar
机构：
[1] Jadavpur University,Department of Electronics & Telecommunication Engineering
来源：
Silicon | 2019年 / 11卷
关键词：
Schottky barrier MOSFET; Tri-gate MOSFETs; Silicon-on-insulator/nothing (SOI/SON); Short channel effects;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The present work centralizes the analytical modeling of a novel structure namely front high-k gate stack Dual-Material Tri-gate Silicon-on-insulator Schottky barrier MOSFET with a dual material bottom gate along with an emphasis on its response towards the various SCEs. 3-D Poisson’s equation along with proper boundary conditions has been solved considering the popular parabolic potential approximation. Different device features like surface potential, threshold voltage, electric field has been studied. Also the device immunity towards the several Short channel effects like drain-induced barrier lowering, threshold voltage roll-off, hot carrier effects are investigated minutely. The analytical results obtained have been verified using simulation results obtained from ATLAS.
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页码：513 / 519
页数：6
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[1]  
Saha P(2017)Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET J Comput Electron Springer 16 648-657
[2]  
Sarkhel S(2004)Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs IEEE Trans Elect Devices 51 569-574
[3]  
Sarkar SK(2017)Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET Microelectron J 67 50-56
[4]  
Kumar MJ(2012)Analysis and design of Tri-Gate MOSFET with high dielectrics gate I J. Int Syst Appl 5 16-22
[5]  
Chaudhry A(2004)Body effect in tri- and pi-gate SOI MOSFETs IEEE Elect Device Lett 25 813-815
[6]  
Banerjee P(2017)Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM AEU-Int J Electron C 80 67-72
[7]  
Sarkar A(2016)Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs Semicond Sci Technol 31 105013-157
[8]  
Sarkar SK(2017)Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications Int J Electron Commun (AEU) 79 151-973
[9]  
Srivastava VM(2014)The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study Adv Nat Sci Nanosci Nanotechnol 5 045015-2289
[10]  
Singh SP(2016)2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs IEEE Trans Elect Devices 63 966-undefined
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