Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

被引：0

作者：

Wei-Wu Hu

Ji-Ye Zhao

Shi-Qiang Zhong

Xu Yang

Elio Guidetti

Chris Wu

机构：

[1] Chinese Academy of Sciences,Key Laboratory of Computer System and Architecture

[2] Chinese Academy of Sciences,Institute of Computing Technology

[3] 39 Chemin du Camp-des-Filles,ST Microelectronics

来源：

Journal of Computer Science and Technology | 2007年 / 22卷

关键词：

general-purpose processor; superscalar pipeline; out-of-order execution; non-blocking cache; physical design; synthesis flow; bit-sliced placement; crafted cell; performance evaluation;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bit-sliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

引用

页码：1 / 14

页数：13