A clock jitter error compensation and auto-tuning structure for continuous-time \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\Upsigma\Updelta$$\end{document} modulators

A novel feedback current compensation structure is proposed to suppress signal-to-noise ratio (SNR) degradation of continuous-time (CT) sigma-delta \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$(\Upsigma\Updelta)$$\end{document} modulators caused by clock jitter. In order to suppress coefficients errors due to process variation, this structure can be reused to automatically tune the integration capacitor to a value with acceptable error. Both the auto-tuning function and jitter error compensation function are suitable for active-RC integrator and Gm-C integrator. This structure is implemented in a third-order single-bit CT\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\Upsigma\Updelta$$\end{document} modulator operating at sampling frequency of 200 MHz and OSR = 48. Compared with modulator without compensation, the SNR is simulated to be improved by 30 dB under a clock jitter of 2.5%. The coefficients of modulator are simulated to be tuned to the value with the error of less than 2.8% under the process variation of 70–130%.