Design of a digitally controlled oscillator for a Delta-Sigma phase-locked loop in a 0.13 µm CMOS-processEntwurf eines digital steuerbaren Oszillators für eine Delta-Sigma Phase-Locked Loop in einem 0,13-μm-CMOS-Prozess

被引：0

作者：

H. Unterassinger

M. Flatscher

Th. Herndl

J. Jongsma

W. Pribyl

机构：

[1] Institut für Elektronik,Technische Universität Graz

[2] Development Center Graz,Infineon Technologies Austria AG

来源：

e & i Elektrotechnik und Informationstechnik | 2010年 / 127卷 / 4期

关键词：

Oscillator; PLL; Frequency synthesis; Oszillator; PLL; Frequenzsynthese;

D O I：

10.1007/s00502-010-0726-1

中图分类号：

学科分类号：

摘要：

In this paper three different oscillator topologies are investigated. The oscillator is to be used in an all-digital phase-locked loop for frequency synthesis for the ISM/SRD license-free frequency bands at 315.0 MHz, 433.9 MHz and 868.3 MHz. The oscillator's frequency range is 75 MHz to 80 MHz and its frequency is controlled via a digital code word.

引用

页码：86 / 90

页数：4