Charge-Plasma-Based Negative Capacitance Ring-FET: Design, Investigation and Reliability Analysis

In this work, an architecture of charge-plasma-based negative capacitance ring-field-effect transistor (ring-NCFET) is proposed and described. Negative capacitance phenomenon is applied to the proposed structure and various parameters such as device characteristics, analog parameters and linearity parameters are analyzed. Negative capacitance helps in scaling down the operating voltage of the proposed device by enhancing the total capacitance and the subthreshold slope. The Landau-Khalatnikov equation was used to attain the effective gate bias across the gate electrode and ferroelectric material. Various calculated device parameters are energy bandgap, electron concentration, hole concentration, electric field variation, potential variation and recombination rate of the dopingless ring-NCFET. The subthreshold slope reduction of 20 mV/decade and approximately twofold increase in drain current at lower gate bias as compared to conventional dopingless ring-FET shows the effectiveness of implementing a negative capacitance technique. Single-gate (SG) dopingless ring-FET (DRing-FET) is compared with SG-DRing-NCFET and double-gate (DG)-DRing-NCFET. The variation of ferroelectric material thickness and interface trap charges (ITCs) is analyzed for device performance optimization and reliability. Various analog/linearity parameters are obtained in the presence of ITCs.