EM-Simulation of Planar Inductor Performance for Epitaxial Silicon Processes

We used a 2.5D EM-simulator to study planar inductor performance in a submicron CMOS technology. We found good agreement between simulations and measurements using only the nominal process parameters for the layer thicknesses, permittivities, and conductivities. By sweeping the thickness and conductivity of the epitaxial layer we show how these parameters affect inductor performance. The presence of a highly conductive substrate layer is shown to have a detrimental effect on inductor performance whereas the thickness and conductivity of the epitaxial layer is less important.