A Low-cost Dithering Method for Improving ADC Linearity Test Applied in uSMILE Algorithm

Analog-to-digital converters (ADCs) are an important component in electronics design. One of the difficulties being faced is to be able to accurately and cost-effectively test the continually higher performance of ADCs under budget constraints. Test time for static linearity is a major portion of the total test cost. Our group proposed an ultrafast segmented model identification of linearity error (uSMILE) algorithm for estimating linearity, which reduces test time dramatically compared to the conventional method. However, this algorithm produces large estimation errors in low resolution ADCs (10-12 bits) when the input is a ramp signal, for which the quantization noise of ADC becomes a dominant part in the total noise. In this study, we propose three types of distribution dithering methods added to the ramp input signal to reduce the estimation error when uSMILE was applied to low resolution ADCs. Fixed pattern was proved to be the most efficient and cost-effective method by comparing with the Gaussian, uniform, and fixed-pattern distributions. The simulation results indicate that the estimation error can be significantly reduced in a 12-bit SAR ADC with effective dithering. Furthermore, a hardware evaluation board with commercial ADC products was used to validate the effectiveness of the fixed-pattern dithering methods, and our measurement shows the INL estimation error can be reduced to less than 0.1 LSB. Such dithering method relaxes the input requirement of uSMILE algorithm which dramatically reduces the test setup cost.