Probability-based static wear-leveling algorithm for block and hybrid-mapping NAND flash memory

被引:0
作者
Yared Hailu Gudeta
Se Jin Kwon
Eun-Sun Cho
Tae-Sun Chung
机构
[1] Ajou University,Department of Computer Engineering
[2] Chungnam National University,Department of Computer Science and Engineering
来源
Design Automation for Embedded Systems | 2012年 / 16卷
关键词
Flash memory; Wear leveling; Embedded system; File system; Flash translation layer;
D O I
暂无
中图分类号
学科分类号
摘要
Owing to its desirable characteristics, flash memory has become attractive to different hardware vendors as a primary choice for data storage. However, because of a limited number of block-erase lifecycles, it has become mandatory to redesign the existing approaches to maximize the flash memory lifetime. Wear-leveling is a mechanism that helps to evenly distribute erase operations to all blocks and enhance lifetime. This research proposes probability-based static wear-leveling. Based on the Markov Chain theory, the future state depends on the present state. Mapping is implemented according to the present visit probability of each logical block in the next state. In each state, the wear-leveling distribution is computed using the standard deviation to determine whether it exceeds the threshold. If it does exceed the threshold, wear-leveling is maintained throughout all blocks in the flash memory by swapping the hot blocks with cold blocks. Using real system-based traces, we have proved that our proposal outperforms the existing design in terms of wear-leveling.
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页码:241 / 264
页数:23
相关论文
共 35 条
[1]  
Kwon SJ(2011)FTL algorithm for NAND-type flash memories Des Autom Embed Syst 15 191-224
[2]  
Ranjitkar A(1999)Moving sequential sectors within a block of information in a flash memory mass storage architecture US Patent 5 930-815
[3]  
Ko YB(2002)A space efficient flash translation layer for compact flash systems IEEE Trans Consum Electron 48 366-375
[4]  
Chung TS(2002)Method of driving remapping in flash memory and flash memory architecture suitable therefore US Patent 6 381-176
[5]  
Estakhri P(2009)A survey of flash translation layer J Syst Archit 55 332-343
[6]  
Iman B(2005)Algorithms and data structures for flash memories ACM Comput Surv 37 138-163
[7]  
Kim J(2010)Improving flash wear-leveling by proactively moving static data IEEE Trans Comput 59 53-65
[8]  
Kim JM(2011)A low-cost wear-leveling algorithm for block-mapping solid-state disks ACM SIGPLAN Not 46 31-40
[9]  
Noh SH(2002)A space-efficient flash translation layer for compact flash systems IEEE Trans Consum Electron 48 366-375
[10]  
Min SL(2011)A hybrid flash translation layer with adaptive merge for SSDs ACM Trans Storage 6 15:1-15:27